1. Field of the Invention
A method for command transmission between systems is disclosed, and more particularly a command transmission between system chips employing a PCI express bus that defines a certain address for transmitting an interrupt or related system management commands.
2. Description of Related Art
The PCI (Peripheral Component Interconnect) local bus interface was introduced by Intel in June of 1992. PCI is an open architecture standard designed to eliminate PC performance bottlenecks by providing a high performance, processor independent data path between the CPU and peripheral devices. Especially in a 32-bit operation computer bus, the transmission speed can reach 133 MB/sec by 33 MHz processing rate, or 266 MB/sec by 66 MHz processing rate.
The next generation of I/O interconnect called PCI Express (briefed as PCI-E) was introduced to enhance transmission speed as a PCI bus meets bandwidth bottlenecks. The PCI Express bus will probably become the standard I/O bus for every operating platform in the future. The lowest transmission speed of a PCI-Express, such as a PCI-E×1, is at least 250 MB/sec rate in single direction and 500 MB/sec rate in bi-direction. Meanwhile the PCI-E×16 reaches 4 GB/sec in single direction or 8 GB/sec in bi-direction transmission rate and the PCI-E×32 can reach 16 GB/sec rate.
The specifications and the related software for the PCI Express bus should involve the attributes of the previous PCI bus. The system bus used for the central processing unit (CPU) of the computer system enhances the working frequency and voltage thereof. Moreover, the bandwidth of the transmission of the memory also steps up, and the transmission bus between system chips, such as the south bridge and the north bridge, are advanced accordingly.
A conventional PCI and the new generation of PCI Express buses are used for the transmission bus among system chips and peripheral devices. The signals under transmission includes at least a memory message, an input/output (I/O) system message, a configuration message, a vendor defined message and the like.
For enhancing the bus rate of transmission of a computer system, the present invention applies the PCI Express bus, which is originally used for the transmission among system chips and peripherals, to the data transmission between system chips or between a CPU and system chips. Therefore, the packet format transmitted under the PCI Express standard should be changed so as to exactly transmit and receive a system management, an interrupt signal or the like among system chips via the PCI Express bus. Since the PCI Express bus extends the conventional structure of the PCI, the preferred embodiment of the present invention can be used to reduce the cost of developing a new transmission interface, and break through the bottleneck of conventional transmission bandwidth.